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mcm63p631a 1 motorola fast sram product preview 64k x 32 bit pipelined burstram synchronous fast static ram the mcm63p631a is a 2m bit synchronous fast static ram designed to pro- vide a burstable, high performance, secondary cache for the 68k family, pow- erpc ? , and pentium ? microprocessors. it is organized as 64k words of 32 bits each. this device integrates input registers, an output register, a 2bit address counter, and high speed sram onto a single monolithic circuit for reduced parts count in cache data ram applications. synchronous design allows precise cycle control with the use of an external clock (k). cmos circuitry reduces the overall power consumption of the integrated functions for greater reliability. addresses (sa), data inputs (dqx), and all control signals except output enable (g ), sleep mode (zz), and linear burst order (lbo ) are clock (k) con- trolled through positiveedgetriggered noninverting registers. bursts can be initiated with either adsp or adsc input pins. subsequent burst addresses can be generated internally by the mcm63p631a (burst sequence operates in linear or interleaved mode dependent upon state of lbo ) and con- trolled by the burst address advance (adv ) input pin. write cycles are internally selftimed and are initiated by the rising edge of the clock (k) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. synchronous byte write (sbx ), synchronous global write (sgw ), and synchro- nous write enable sw are provided to allow writes to either individual bytes or to all bytes. the four bytes are designated as aao, abo, aco, and ado. sba controls dqa, sbb controls dqb, etc. individual bytes are written if the selected byte writes sbx are asserted with sw . all bytes are written if either sgw is asserted or if all sbx and sw are asserted. for read cycles, pipelined srams output data is temporarily stored by an edgetriggered output register and then released to the output buffers at the next rising edge of clock (k). the mcm63p631a operates from a 3.3 v power supply, all inputs and outputs are lvttl compatible. ? mcm63p631a117 = 4.5 ns access / 8.5 ns cycle (117 mhz) mcm63p631a100 = 4.5 ns access / 10 ns cycle (100 mhz) mcm63p631a75 = 7 ns access / 13.3 ns cycle (75 mhz) mcm63p631a66 = 8 ns access / 15 ns cycle (66 mhz) ? single 3.3 v + 10%, 5% power supply ? adsp , adsc , and adv burst control pins ? selectable burst sequencing order (linear/interleaved) ? internally selftimed write cycle ? byte write and global write control ? sleep mode (zz) ? pb1 version 2.0 compatible ? singlecycle deselect timing ? jedec standard 100pin tqfp package the powerpc name is a trademark of ibm corp., used under license therefrom. pentium is a trademark of intel corp. this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by mcm63p631a/d semiconductor technical data mcm63p631a tq package tqfp case 983a01 9/30/97 ? motorola, inc. 1997
mcm63p631a 2 motorola fast sram functional block diagram write register a write register b enable register burst counter adsp g clr write register c write register d sba sbb sbc sbd se3 14 16 sgw dataout register enable register k2 k address register 16 datain register 64k x 32 array se2 lbo adv k adsc sa sa1 sa0 sw se1 k 4 32 2 2 k2 dqa dqd 32 zz
mcm63p631a 3 motorola fast sram pin assignment 71 72 dqc v dd nc 69 70 66 67 68 64 65 61 62 63 37 38 34 35 36 42 43 39 40 41 45 46 44 60 59 58 57 56 55 54 53 52 51 31 32 33 74 75 76 77 78 79 80 50 49 48 47 dqb dqb v ss dqb dqb dqb dqb v ss v dd dqb dqb v dd v ss v ss v dd dqc dqc dqc dqc dqc dqc dqc nc sa sa se1 sbd k sbc adv g adsc adsp sa0 sa sa sa sa nc nc nc nc v ss lbo sa1 v dd v dd nc dqa v ss dqa dqa dqa dqa v ss v dd dqa dqa v ss v dd nc dqa dqd v dd v ss v ss v dd dqd dqd dqd dqd dqd 73 nc 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 sa sa sw se2 sbb sba se3 v ss v dd sgw zz nc v dd v ss dqd dqd nc sa nc sa sa sa sa sa
mcm63p631a 4 motorola fast sram pin descriptions pin locations symbol type description 85 adsc input synchronous address status controller: active low, is used to latch a new external address. used to initiate a read, write or chip deselect. 84 adsp input synchronous address status processor: initiates read or chip deselect cycle (exception e chip deselect does not occur when adsp is asserted and se1 is high). 83 adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79 (c) 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 86 g input asynchronous output enable. 89 k input clock: this signal registers the address, data in, and all control signals except g , lbo , and zz. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter (68k/powerpc). high e interleaved burst counter (486/i960/pentium). 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b, c, d). sgw overrides sbx . 98 se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 87 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 64 zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. 4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 v dd supply power supply: 3.3 v + 10%, 5%. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 1, 14, 16, 30, 38, 39, 42, 43, 50, 51, 66, 80 nc e no connection: there is no connection to the chip.
mcm63p631a 5 motorola fast sram truth table (see notes 1 through 5) next cycle address used se1 se2 se3 adsp adsc adv g 3 dqx write 2, 4 deselect none 1 x x x 0 x x highz x deselect none 0 x 1 0 x x x highz x deselect none 0 0 x 0 x x x highz x deselect none x x 1 1 0 x x highz x deselect none x 0 x 1 0 x x highz x begin read external 0 1 0 0 x x x highz read 5 begin read external 0 1 0 1 0 x x highz read 5 continue read next x x x 1 1 0 1 highz read continue read next x x x 1 1 0 0 dq read continue read next 1 x x x 1 0 1 highz read continue read next 1 x x x 1 0 0 dq read suspend read current x x x 1 1 1 1 highz read suspend read current x x x 1 1 1 0 dq read suspend read current 1 x x x 1 1 1 highz read suspend read current 1 x x x 1 1 0 dq read begin write external 0 1 0 1 0 x x highz write continue write next x x x 1 1 0 x highz write continue write next 1 x x x 1 0 x highz write suspend write current x x x 1 1 1 x highz write suspend write current 1 x x x 1 1 x highz write notes: 1. x = don't care. 1 = logic high. 0 = logic low. 2. write is defined as either 1) any sbx and sw low or 2) sgw is low. 3. g is an asynchronous signal and is not sampled by the clock k. g drives the bus immediately (t glqx ) following g going low. 4. on write cycles that follow read cycles, g must be negated prior to the start of the write cycle to ensure proper write data setup times. g must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. this read assumes the ram was previously deselected.
mcm63p631a 6 motorola fast sram asynchronous truth table operation zz g i/o status read l l data out (dqx) read l h highz write l x highz deselected l x highz sleep h x highz linear burst address table (lbo = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (lbo = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00 write truth table cycle type sgw sw sba sbb sbc sbd read h h x x x x read h l h h h h write byte a h l l h h h write byte b h l h l h h write byte c h l h h l h write byte d h l h h h l write all bytes h l l l l l write all bytes l x x x x x
mcm63p631a 7 motorola fast sram absolute maximum ratings (see note 1) rating symbol value unit notes power supply voltage v dd 0.5 to + 4.6 v voltage relative to v ss for any pin except v dd v in , v out 0.5 to v dd + 0.5 v output current (per i/o) i out 20 ma package power dissipation p d 1.6 w 2 ambient temperature t a 0 to 70 c die temperature t j 110 c 2 temperature under bias t bias 10 to 85 c storage temperature t stg 55 to 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. power dissipation capability is dependent upon package characteristics and use environment. see package thermal characteristics. package thermal characteristics rating symbol max unit notes junction to ambient (@ 200 lfm) single layer board four layer board r q ja 40 25 c/w 1, 2 junction to board (bottom) r q jb 17 c/w 3 junction to case (top) r q jc 9 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit.
mcm63p631a 8 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t a = 0 to 70 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.6 v input low voltage v il 0.5 e 0.8 v input high voltage v ih 2.0 e v dd + 0.5 v dc characteristics and supply currents parameter symbol min typ max unit notes input leakage current (0 v v in v dd ) i lkg (i) e e 1 m a 1, 2 output leakage current (0 v v in v dd ) i lkg (o) e e 1 m a ac supply current (device selected, all outputs open, mcm63p631a117 freq = max, v dd = max) mcm63p631a100 mcm p a i dda e e e e tbd ma 3, 4, 5 q dd ) mcm63p631a75 mcm63p631a66 e e e e cmos standby supply current (device deselected, freq = 0, v dd = max, all inputs static at cmos levels) i sb2 e e tbd ma 6, 7 sleep mode supply current (sleep mode, freq = max, v dd = max, all other inputs static at cmos levels, zz v dd 0.2 v) i zz e e 2 ma 2, 7, 8 ttl standby (device deselected, freq = 0, v dd = max, all inputs static at ttl levels) i sb3 e e tbd ma 6, 9 clock running (device deselected, freq = max, mcm63p631a117 v dd = max, all inputs toggling at cmos levels) mcm63p631a100 mcm p a i sb4 e e e e tbd ma 6, 7 dd pggg ) mcm63p631a75 mcm63p631a66 e e e e static clock running (device deselected, freq = max, mcm63p631a117 v dd = max, all inputs static at ttl levels) mcm63p631a100 mcm63p631a75 mcm63p631a66 i sb5 e e e e e e e e tbd ma 6, 9 output low voltage (i ol = 8 ma) v ol e e 0.4 v output high voltage (i oh = 4 ma) v oh 2.4 e e v notes: 1. lbo pin has an internal pullup and will exhibit leakage currents of 5 m a. 2. zz pin has an internal pulldown and will exhibit leakage currents of 5 m a. 3. reference ac operating conditions and characteristics for input and timing (v ih /v il , t r /t f , pulse level 0 to 3.0 v). 4. all addresses transition simultaneously low (lsb) and then high (msb). 5. data states are all zero. 6. device in deselected mode as defined by the truth table. 7. cmos levels are v in v ss + 0.2 v or v dd 0.2 v. 8. device in sleep mode as defined by the asynchronous truth table. 9. ttl levels are v in v il or v ih . capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol min typ max unit input capacitance c in e 3 5 pf input/output capacitance c i/o e 6 8 pf
mcm63p631a 9 motorola fast sram ac operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t a = 0 to 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20 to 80%) . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1 unless otherwise noted . . . . . . . . . . . . . . read/write cycle timing (see notes 1, 2, 3, and 4) 63p631a117 117 mhz 63p631a100 100 mhz 63p631a75 75 mhz 63p631a66 66 mhz parameter symbol min max min max min max min max unit notes cycle time t khkh 8.5 e 10 e 13 e 15 e ns clock high pulse width t khkl 3.4 e 4 e 5.2 e 6 e ns clock low pulse width t klkh 3.4 e 4 e 5.2 e 6 e ns clock access time t khqv e 4.5 e 4.5 e 7 e 8 ns output enable to output valid t glqv e 4.5 e 4.5 e 5 e 5 ns clock high to output active t khqx1 0 e 0 e 0 e 0 e ns 5 clock high to output change t khqx2 1.5 e 1.5 e 1.5 e 1.5 e ns 5 output enable to output active t glqx 0 e 0 e 0 e 0 e ns 5 output disable to q highz t ghqz e 5.5 e 5.5 e 7 e 8 ns 5, 6 clock high to q highz t khqz 1.5 5.5 1.5 5.5 2 7 2 8 ns 5, 6 setup times: address adsp , adsc , adv data in write chip enable t adkh t adskh t dvkh t wvkh t evkh 2.5 e 2.5 e 2.5 e 2.5 e ns hold times: address adsp , adsc , adv data in write chip enable t khax t khadsx t khdx t khwx t khex 0.5 e 0.5 e 0.5 e 0.5 e ns sleep mode standby t zzs e 2 x t khkh e 2 x t khkh e 2 x t khkh e 2 x t khkh ns sleep mode recovery t zzrec 2 x t khkh e 2 x t khkh e 2 x t khkh e 2 x t khkh e ns sleep mode high to q highz t zzqz e 15 e 15 e 15 e 15 ns notes: 1. write applies to all sbx , sw , and sgw signals when the chip is selected and adsp high. 2. chip enable applies to all se1 , se2 and se3 signals whenever adsp or adsc is asserted. 3. all read and write cycle timings are referenced from k or g . 4. g is a don't care after write cycle begins. to prevent bus contention, g should be negated prior to start of write cycle. 5. this parameter is sampled and is not 100% tested. 6. measured at 200 mv from steady state. output z 0 = 50 w r l = 50 w v t = 1.5 v figure 1. ac test load
mcm63p631a 10 motorola fast sram burst read single read adsc t khkl t khkh dqx e k adsp adv q(a) burst write adsp, sa sa ab read/write cycles t klkh cd se1 w q(b) q(b+1) t khqv burst wraps around q(b+2) q(b+3) q(b) d(c) d(c+1) d(c+2) d(c+3) q(d) t khqv deselected single read se2, se3 ignored g t khqx1 t khqx2 t ghqz t glqx w low = sgw low and / or sw and sbx low. note: e low = se2 high and se3 low. q(n1) t khqz
zz e k ads adv sleep mode timing w g t zzqz ads high = both adsc, adsp high. note: ads low = adsc low or adsp low. idd t zzs t zzrec e low = se1 low, se2 high, se3 low. addr dq normal operation no reads or writes allowed in sleep mode no new reads or writes allowed normal operation i zz i (max) specifications will not be met if inputs toggle. zz mcm63p631a 11 motorola fast sram
mcm63p631a 12 motorola fast sram application information the mcm63p631a burstram is a high speed synchro- nous sram intended for use primarily in secondary or level two (l2) cache memory applications. l2 caches are found in a variety of classes of computers e from the desktop per- sonal computer to the highend servers and transaction pro- cessing machines. for simplicity, the majority of l2 caches today are direct mapped and are single bank implementa- tions. these caches tend to be designed for bus speeds in the range of 33 to 66 mhz. at these bus rates, nonpipelined (flowthrough) burstrams can be used since their access times meet the speed requirements for a minimumlatency, zerowait state l2 cache interface. latency is a measure (time) of adeado time the memory system exhibits as a result of a memory request. for those applications that demand bus operation at great- er than 66 mhz or multibank l2 caches at 66 mhz, the pipe- lined (register/register) version of the 64k x 32 burstram (mcm63p631a) allows the designer to maintain zerowait state operation. multiple banks of burstrams create addi- tional bus loading and can cause the system to otherwise miss its timing requirements. the access time (clocktoval- iddata) of a pipelined burstram is inherently faster than a nonpipelined device by a few nanoseconds. this does not come without cost. the cost is latency e adeado time. since most l2 caches are tied to the processor bus and bus speeds continue to increase over time, pipelined (r/r) burstrams are the best choice in achieving zerowait state l2 cache performance. for costsensitive applications that require zerowait state l2 cache bus speeds of up to 75 mhz, pipelined burstrams are able to provide fast clock to valid data times required of these high speed buses. sleep mode a sleep mode feature, the zz pin, has been implemented on the mcm63p631a. it allows the system designer to place the ram in the lowest possible power condition by asserting zz. the sleep mode timing diagram shows the different modes of operation: normal operation, no read/write allowed, and sleep mode. each mode has its own set of constraints and conditions that are allowed. normal operation: all inputs must meet setup and hold times prior to sleep and t zzrec nanoseconds after recovering from sleep. clock (k) must also meet cycle, high, and low times during these periods. two cycles prior to sleep, initiation of either a read or write operation is not al- lowed. no read/write: during the period of time just prior to sleep and during recovery from sleep, the assertion of either adsc , adsp , or any write signal is not allowed. if a write operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram can not be guaranteed immediately after zz is asserted (prior to be- ing in sleep). sleep mode: the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep cur- rent (i zz ). all inputs are allowed to toggle e the ram will not be selected and perform any reads or writes. however, if in- puts toggle, the i zz (max) specification will not be met. nonburst synchronous operation although this burstram has been designed for powerpc and pentiumbased systems, these srams can be used in other high speed l2 cache or memory applications that do not require the burst address feature. most l2 caches de- signed with a synchronous interface can make use of the mcm63p631a. the burst counter feature of the burstram can be disabled, and the sram can be configured to act upon a continuous stream of addresses. see figure 2. control pin tie values (h v ih , l v il ) nonburst adsp adsc adv se1 lbo sync nonburst, pipelined sram h l h l x note: alt hough x is specified in the table as a don't care, the pin must be tied either high or low.
mcm63p631a 13 motorola fast sram writes reads dqx k q(b) q(a) addr ab cd ef gh w q(d) q(c) d(f) d(e) d(h) d(g) g figure 2. configured as nonburst pipelined synchronous sram
mcm63p631a 14 motorola fast sram ordering information (order by full part number) mcm 63p631a xx x x motorola memory prefix part number full part numbers e mcm63p631atq117 mcm63p631atq100 mcm63p631atq117r mcm63p631atq100r mcm63p631atq75 mcm63p631atq66 mcm63p631atq75r mcm63p631atq66r speed (117 = 117 mhz, 100 = 100 mhz, 75 = 75 mhz, 66 = 66 mhz) package (tq = tqfp) blank = trays, r = tape and reel
mcm63p631a 15 motorola fast sram tq package tqfp case 983a01 package dimensions dim min max min max inches millimeters a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 b1 0.22 0.33 0.009 0.013 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 d 22.00 bsc 0.866 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 l1 1.00 ref 0.039 ref l2 0.50 ref s 0.20 0.008 r1 0.08 0.003 r2 0.08 0.20 0.003 0.008 0 7 0 7 0 0 11 13 11 13 11 13 11 13 1 2 3 d1 20.00 bsc 0.787 bsc 0.020 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d
mcm63p631a 16 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan: nippon motorola ltd.; spd, strategic planning office; 4-32-1, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 nishi-gotanda; shinagawa-ku, tokyo 141, japan. 81-3-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & c anada only 1-800-774-1848 51 ting kok road, tai po, n.t., hong kong. 852-26629298 http ://sps.motorola.com /mfax / home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm63p631a/d ?

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